The application relates generally to substrate processing methods and particularly to process sequences which increase the density of features on the substrate.
Shrinking integrated circuits (ICs) may result in improved performance, increased capacity and/or reduced cost. Each device shrink requires more sophisticated techniques to form the features. Photolithography is commonly used to pattern features on a substrate. An exemplary feature is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two neighboring lines. The pitch is equal to the sum of the linewidth and the spacing. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
Self-aligned double patterning (SADP) is one method for extending the capabilities of photolithographic techniques beyond their supposed minimum pitch. Such a method is illustrated in FIGS. 1A-H. With reference to FIG. 1A, photolithography is used to produce a pattern of lines 114 in a photoresist layer on a sacrificial structural layer 105 formed on a substrate 100. As shown in FIG. 1B, the pattern is then transferred into sacrificial structural layer 105 using an etching process to form features referred to as placeholders, mandrels or cores 106. The photoresist lines 114 are then stripped (FIG. 1C), and conformal layer 120 of material is subsequently deposited over cores 106, as shown in FIG. 1D. Spacers 121 are then formed on the sides of cores 106 by preferentially etching the conformal material from the horizontal surfaces with an anisotropic spacer etch. The resulting structure is shown in FIG. 1E. Cores 106 may then be removed, leaving behind spacers 121 (FIG. 1F). At this point the spacers 121 may be used as an etch mask for patterning the substrate, as shown in FIG. 1G, and subsequently removed (FIG. 1H). Thus, where a given pitch of the patterned photoresist 114 included one feature, the same width now includes two features. With no change in lithographic linewidth, the pitch has been reduced.
The SADP method described above allows the spacing between adjacent lines or features to be varied but typically produces features of only a single width for a given thickness of the original conformal layer 120. Other SADP techniques, for example a negative tone version of the process of the SADP method described in FIGS. 1A-1H, allow variable width features that are spaced apart from each other by only one spacing distance.
Many integrated circuits employ features of different widths and spacing distances (spacings). Thus, some SADP techniques have been developed that employ multiple high-resolution photomasks to fabricate features of different widths and/or allow different spacings between adjacent features. Employing multiple high-resolution photomasks present alignment challenges and increase manufacturing costs.